1. Field of the Invention
The present invention relates to a semiconductor chip assembly, and more particularly to a method of mechanically and electrically connecting a conductive trace to a semiconductor chip.
2. Description of the Related Art
Semiconductor chips have input/output pads that must be connected to external circuitry in order to function as part of an electronic system. The connection media is typically an array of metallic leads (e.g., a lead frame) or a support circuit (e.g., a substrate), although the connection can be made directly to a circuit panel (e.g., a mother board). Several connection techniques are widely used. These include wire bonding, tape automated bonding (TAB) and flip-chip bonding.
Wire bonding is by far the most common and economical connection technique. In this approach, wires are bonded, one at a time, from the chip to external circuitry by thermocompression, thermosonic or ultrasonic processes. In thermocompression bonding, fine gold wire is fed from a spool through a clamp and a capillary. A thermal source is swept past an end of the wire to form a wire ball that protrudes from the capillary. The chip or capillary is then heated to about 200 to 300xc2x0 C., the capillary is brought down over an aluminum pad, the capillary exerts pressure on the wire ball, and the wire ball forms a ball bond on the pad. The capillary is then raised and moved to a terminal on the support circuit, the capillary is brought down again, and the combination of force and temperature forms a wedge bond between the wire and the terminal. Thus, the connection between the pad and the terminal includes the ball bond (which only contacts the pad), the wedge bond (which only contacts the terminal) and the wire between the bonds. After raising the capillary again, the wire is ripped from the wedge bond, the thermal source is swept past the wire to form a new wire ball, and the process is repeated for other pads on the chip. Thermosonic bonding is similar to thermocompression bonding but adds ultrasonic vibration as the ball and wedge bonds are formed so that less heat is necessary. Ultrasonic bonding uses aluminum wire to form wedge bonds without applying heat. There are many variations on these basic methods.
TAB involves bonding gold-bumped pads on the chip to external circuitry on a polymer tape using thermocompression bonding. TAB requires mechanical force such as pressure or a burst of ultrasonic vibration and elevated temperature to accomplish metallurgical welding between the wires or bumps and the designated surface.
Flip-chip bonding involves providing pre-formed solder bumps on the pads, flipping the chip so that the pads face down and are aligned with and contact matching bond sites, and melting the solder bumps to wet the pads and the bond sites. After the solder reflows it is cooled down and solidified to form solder joints between the pads and the bond sites. Organic conductive adhesive bumps with conductive fillers in polymer binders have been used in place of solder bumps, but they do not normally form a metallurgical interface in the classical sense. A major advantage of flip-chip bonding over wiring bonding and TAB is that it provides shorter connection paths between the chip and the external circuitry, and therefore has better electrical characteristics such as less inductive noise, cross-talk, propagation delay and waveform distortion. In addition, flip-chip bonding requires minimal mounting area and weight which results in overall cost saving since no extra packaging and less circuit board space are used.
While flip-chip technology has tremendous advantages over wire bonding and TAB, its cost and technical limitations are significant. For instance, the cost of forming bumps on the pads is significant. In addition, an adhesive is normally underfilled between the chip and the support circuit to reduce stress on the solder joints due to thermal mismatch between the chip and the support circuit, and the underfilling process increases both manufacturing complexity and cost. Furthermore, the solder joints exhibit increased electrical resistance as well as cracks and voids over time due to fatigue from thermo-mechanical stresses. Finally, the solder is typically a tin-lead alloy and lead-based materials are becoming far less popular due to environmental concerns over disposing of toxic materials and leaching of toxic materials into ground water supplies.
Other techniques besides wire bonding, TAB and flip-chip bonding have been developed to connect chips to external circuitry without using wires, leads or bumps. Such techniques include thin film rerouting at the wafer, panel or module level, and attaching a pre-patterned substrate to the chip such that through-holes in the substrate expose the pads and selectively applying conductive material into the through-holes.
A typical thin film routing approach includes depositing a dielectric material on the chip, providing through-holes in the dielectric material that expose the pads, providing metallization in the through-holes that contacts the pads, and providing a top layer of conductive circuitry on the dielectric material that contacts the metallization. In this manner, the additional circuitry is fabricated on the chip. Drawbacks to this approach include complicated manufacturing requirements, high cost, and chip loss if the additional circuitry is defective. In particular, since the chip or wafer provides a substrate for the additional circuitry, chips will be lost if the additional circuitry fails to achieve certain quality and yield criteria. Unpredictable chip loss has prevented the wide spread adoption of this xe2x80x9cchip firstxe2x80x9d approach in volume production. Furthermore, if the process is not performed on wafers, the commercially available silicon wafer processing equipment may not be compatible with common tooling and handling techniques.
Conductive adhesives that electrically connect pads on chips to conductive traces on support circuits are well-known in the art. As mentioned above, organic conductive adhesive bumps with conductive fillers in polymer binders have been used, but they do not normally form a metallurgical interface in the classical sense. Moisture penetration through the polymer binder may induce corrosion or oxidation of the conductive filler particles resulting in an unstable electrical connection. Furthermore, the polymer binder and the conductive filler may degrade leading to an unstable electrical connection. Thus, the conductive adhesive may have adequate mechanical strength but poor electrical characteristics.
In view of the various development stages and limitations in currently available semiconductor chip assemblies, there is a need for a semiconductor chip assembly that is cost-effective, reliable, manufacturable, provides excellent mechanical and electrical performance, and complies with stringent environmental standards.
An object of the present invention is to provide a semiconductor chip assembly with a chip and a conductive trace that provides a low cost, high performance, high reliability package.
Another objective of the present invention is to provide a convenient, cost-effective method for manufacturing semiconductor chip assemblies as chip scale packages, chip size packages, ball grid arrays or other structures.
In accordance with one aspect of the invention, a semiconductor chip assembly includes a semiconductor chip, a conductive trace, a connection joint, and an insulative adhesive. The conductive trace includes a routing line and a pillar. The connection joint contacts and electrically connects the routing line and the pad.
In one embodiment, the adhesive is sandwiched between the routing line and the chip and contacts a surface of the routing line that faces away from the chip, thereby interlocking the routing line to the assembly.
In another embodiment, the pillar extends outside a periphery of the chip, and an encapsulant extends into a channel in the pillar, thereby interlocking the pillar to the assembly.
In accordance with another aspect of the invention, a method of making a semiconductor chip assembly includes attaching a chip to a metallic structure using an insulative adhesive, wherein the chip includes a conductive pad, and the metallic structure includes a metal base, a first metal pattern and a second metal pattern, the first metal pattern is disposed on a side of the metal base that faces away from the chip, and the second metal pattern is disposed on a side of the metal base that faces towards the chip, then etching the metal base, thereby exposing the second metal pattern, and then forming a connection joint that contacts and electrically connects the second metal pattern and the pad.
The method may include electroplating the first and second metal patterns on the metal base before attaching the chip to the metallic structure, and etching the adhesive thereby exposing the pad after etching the metal base and before forming the connection joint.
The method may also include etching the metal base by applying a wet chemical etch using the first metal pattern as an etch mask to remove all of the metal base above the pad without removing a portion of the metal base outside the pad such that the remaining portion of the metal base provides the pillar and the second metal pattern provides the routing line, and then removing the first metal pattern.
The method may also include etching the metal base using the second metal pattern as an etch mask, thereby forming an undercut channel in the metal base that exposes a portion of the second metal pattern that faces away from the chip and towards the metal base, and then filling the adhesive into the undercut channel, thereby enhancing the mechanical attachment between the second metal pattern and the adhesive.
The method may also include etching the metal base using the second metal pattern as an etch mask after attaching the chip to the metallic structure using the adhesive, thereby forming an undercut channel in the metal base that exposes a portion of the second metal pattern that faces away from the chip and towards the metal base, and then filling the encapsulant into the undercut channel, thereby enhancing the mechanical attachment between the second metal pattern and the encapsulant.
An advantage of the present invention is that the semiconductor chip assembly need not include wire bonds, TAB leads or solder joints. Another advantage is that the conductive trace can be interlocked by the adhesive and/or encapsulant. Another advantage is that the pillar can be formed using etching (i.e., subtractively) rather than by electroplating or electroless plating (i.e., additively) which improves uniformity and reduces manufacturing time and cost. Another advantage is that the assembly can be manufactured using low temperature processes which reduces stress and improves reliability. A further advantage is that the assembly can be manufactured using well-controlled wet chemical processes which can be easily implemented by circuit board, lead frame and tape manufacturers. Still another advantage is that the assembly can be manufactured using materials that are compatible with copper chip and lead-free environmental requirements.
These and other objects, features and advantages of the invention will be further described and more readily apparent from a review of the detailed description of the preferred embodiments which follows.